This invention relates to the fabrication of semiconductor integrated circuits, and in particular to a method of forming electrically isolated areas in the semiconductor material.
In the fabrication of bipolar integrated circuits, the semiconductor wafer is typically a three tier structure, with a p-type substrate, an n.sup.+ region serving as a low resistance contact or collector region which is formed either as an isolated region or an epitaxial layer over the entire surface of the substrate, and an n-type or p-type epitaxial layer formed over the n.sup.+ region, which n-type epitaxial layer serves as the active region of the devices and the p-type layer serves as the bases of transistors. An important, and often troublesome, step in the fabrication of circuits is the electrical isolation of portions of these epitaxial layers.
One method currently being used involves diffusing opposite conductivity type impurities through the epitaxial layer or layers to form an isolating region extending to the p-type substrate in the case of the n-type epitaxial layer or to the n.sup.+ type collector in the case of the p-type epitaxial layer and surrounding the desired isolated area (see, for example, U.S. Pat. No. 3,648,125, issued to Peltzer). Another basic approach is to etch channels to the p substrate around the area to be isolated and then fill the channels with oxide (see, for example, U.S. Pat. No. 4,056,415, issued to Cook). The major drawback of both these methods is that the isolating regions take up a large area of the semiconductor and do not permit closely packed structures. Further, the junction isolation technique adds sidewall capacitance to the circuit, while the oxide-filled channel approach is usually restricted to shallow structures and often requires long oxidation which can cause undesired stresses.
In the prior art methods, the buried low resistance contact is usually formed in selective areas of the substrate and contact is made thereto from the surface by diffused regions. Such a technique requires additional masking and diffusion operations if a low resistance contact is required, and also contributes further to the problem of utilizing too much semiconductor area, since the diffusions from the surface have to be deep enough to penetrate the top layer and the resulting width of the diffused regions is quite large. It would be more desirable to form the buried contact or collector by means of a layer covering the entire surface of the substrate, thereby eliminating a masking operation, and to make contact to such a layer from the surface of the wafer with a shallow diffusion.
It is also advantageous to provide p.sup.+ regions as a means of preventing inversion of portions of the p substrate which are exposed by etching channels, and incorporating formation of such means with the remainder of the processing in a manner which will conserve space and limit the number of masking operations. Such regions are often referred to as "chanstop" regions.
The invention is therefore directed to the problem of providing a method for isolating portions of a three layer semiconductor wafer which permits contact to a buried layer and formation of chanstop regions while utilizing a minimum of semiconductor area and therefore permitting closely packed structures.